Integrated circuits, including computer chips, are manufactured by building up layers of circuits on the front side of silicon wafers. An extremely high degree of wafer flatness and layer flatness is required during the manufacturing process. Chemical-mechanical planarization (CMP) is a process used during device manufacturing to flatten wafers and the layers built-up on wafers to the necessary degree of flatness.
Chemical-mechanical planarization is a process involving polishing of a wafer with a polishing pad combined with the chemical and physical action of a slurry pumped onto the pad. The wafer is held by a wafer carrier, with the backside of the wafer facing the wafer carrier and the front side of the wafer facing a polishing pad. The polishing pad is held on a platen, which is usually disposed beneath the wafer carrier. Both the wafer carrier and the platen are rotated so that the polishing pad polishes the front side of the wafer. A slurry of selected chemicals and abrasives is pumped onto the pad to affect the desired type and amount of polishing. (CMP is therefore achieved by a combination of chemical softener and physical downward force that removes material from the wafer or wafer layer.) The downward force, referred to in this application as the Spindle Force, is split in the wafer carrier to a Retaining Ring Force and a Wafer Force.
Using the CMP process, a thin layer of material is removed from the front side of the wafer or wafer layer. The layer may be a layer of oxide grown or deposited on the wafer or a layer of metal deposited on the wafer. The removal of the thin layer of material is accomplished so as to reduce surface variations on the wafer. Thus, the wafer and layers built-up on the wafer are very flat and/or uniform after the process is complete. Typically, more layers are added and the chemical mechanical planarization process repeated to build complete integrated circuit chips on the wafer surface.
A variety of wafer carrier configurations are used during CMP. One such wafer carrier configuration is the hard backed configuration. The hard backed configuration utilizes a rigid surface such as a piston or backing plate against the backside of the silicon wafer during CMP forcing the front surface of the silicon wafer to the surface of the polishing pad. Using this type of carrier may not conform the front wafer surface of the wafer to the surface of the polishing pad resulting in planarization non-uniformities. Such hard backed wafer carrier designs generally utilize a relatively high polishing pressure. These relatively high pressures effectively deform the wafer to match the surface conformation of the polishing pad. When wafer surface distortion occurs, the high spots are polished at the same time as the low spots giving some degree of uniformity but also resulting in poor planarization. Too much material from some areas of the wafer will be removed and too little material from other areas will also be removed. In addition to wafer distortion, the relatively high pressure also results in excessive material removal along the edges of the silicon wafer. When the amount of material removed is excessive, the entire wafer or portions of the wafer become unusable.
In other wafer carrier configurations, the wafer is pressed against the polishing pad using a membrane or other soft material. Use of a membrane carriers tend to not cause distortion of the wafer. Lower polishing pressures may be employed, and conformity of the wafer front surface is achieved without distortion so that both some measure of global polishing uniformity and good planarization may be achieved. Better planarization uniformity is achieved at least in part because the polishing rate on similar features from die to die on the wafer is the same.
While many soft backed wafer carrier configurations are used in CMP, their use has not been entirely satisfactory. In some carrier designs, there have been attempts to use a layer of pressurized air over the entire surface of the wafer to press the wafer during planarization. Unfortunately, while such approaches may provide a soft back for the wafer carrier, it does not permit independent adjustment of the pressure at the edge of the wafer and at more central regions of the wafer to solve the wafer edge non-uniformity problems.
In order to correct or compensate for edge polishing effects, attempts have been made to adjust the shape of the retaining ring and to modify a retaining ring pressure so that the amount of material removed from the wafer near the retaining ring was modified. Typically, more material is removed from the edge of the wafer resulting in over polishing. In order to correct this over polishing, usually, the retaining ring pressure is adjusted to be somewhat lower than the wafer backside pressure so that the polishing pad in that area was somewhat compressed by the retaining ring and less material was removed from the wafer within a few millimeters of the retaining ring. These attempts, however, have not been entirely satisfactory as the planarization pressure at the outer peripheral edge of the wafer was only indirectly adjustable based on the retaining ring pressure. It was not possible to extend the effective distance of a retaining ring compensation effect an arbitrary distance into the wafer edge. Neither was it possible to independently adjust the retaining ring pressure, edge pressure, or independently adjust backside wafer pressure with respect to retaining ring pressure to achieve a desired result.
There remains a need for a membrane backed wafer carrier having independent control of both the membrane pressure and retaining ring pressure providing excellent planarization, control of edge planarization effects, and adjustment of the wafer material removal profile to compensate for non-uniform deposition of the structural layers on the wafer semiconductor substrate.